1. Field of the Invention
The present invention relates to a method for manufacturing a semiconductor device using a spin on glass (SOG) layer
2. Description of the Related Art
With the development of integrated circuit devices such as a dynamic random access memory (DRAM) device, a three-dimensional construction has been adopted. As a result, the surfaces of layers forming the device have become uneven, thus creating short-circuits and disconnections of wiring patterns. On the other hand, in a photolithography apparatus, i.g., a stepper, as devices have become more fine-structured, the numerical aperture of a lens has been increased and the wavelength of light has been decreased, so that the focus depth has become shallow. Therefore, the flat characteristics of each layer have become more important.
In a first prior art method for manufacturing a semiconductor device, a boron-included phosphorus-silicated glass (BPSG) layer is formed by an atmospheric chemical vapor deposition (CVD) process, and the BPSG layer is annealed at a high temperature to reflow it. Thus, the surface of the BPSG layer is flattened. This is advantageous in that it is a simple process.
In the first prior art method, however, if the reflowing temperature is reduced, it is impossible to reflow the BPSG layer. Therefore, the reflowing temperature needs to be high, thus enlarging the junction depth of the device. This is disadvantageous for obtaining a fine structure.
In a second prior art method for manufacturing a semiconductor device, if an uneven insulating layer is formed, an SOG solution is spin-coated on the uneven insulating layer to form an SOG layer thereon. Then, the SOG layer is etched back, so that the surface of the SOG layer as well as the insulating layer is flattened.
In the second prior art method, however, when a contact hole is perforated in the SOG layer and the insulating layer which are flattened, the SOG layer is exposed, so that the SOG layer is in contact with a conductive layer buried in the contact hole. Therefore, water of the SOG layer reacts with the conductive layer, so that the conductive layer is eroded. Thus, short-circuits and disconnections of the conductive layer may be invited.
In order to separate the conductive layer buried in the contact hole from the SOG layer in the second prior art method, in a third prior art method for manufacturing a semiconductor device (see JP-A-7-74248), a dummy insulating pattern layer is formed on a portion of the insulating layer where the above-mentioned contact hole will be formed. As a result, the dummy insulating pattern layer is located between the conductive layer and the SOG layer. Therefore, water of the SOG layer hardly reacts with the conductive layer, so that the conductive layer is not eroded. Thus, short-circuits and disconnections of the conductive layer can be avoided. This will be explained later in detail.
In the third prior art method, however, the flat characteristics of the etched SOG layer including the dummy insulating pattern layer are actually deteriorated. That is, in order to completely remove the part of the SOG layer on the dummy insulating pattern layer, an overetching of the SOG layer is required. Note that the etching rate of the SOG layer is usually larger than that of the dummy insulating pattern layer. As a result, a large step between the etched SOG layer and the dummy insulating pattern layer is generated, thus deteriorating the flat characteristics of the etched SOG layer including the dummy insulating pattern layer.
In addition, in the third prior art method, an additional process for forming the dummy insulating pattern layer is required, thus increasing the manufacturing cost.